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| HFC0300 variable off time controller hfc030 0 rev. 1 . 0 www.monolithicpower.com 1 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic technology descri ption HFC0300 is a variable off-time co ntroller that uses a f i xed-peak?current technique to decrease its frequency as the load lightens. as a result, it of fers excelle nt efficien cy at light-load while optimizing the efficiency under other load conditions. when the f r equency decreases to threshold , the peak cu rrent decrea s es with the decreasing load to prevent mechanical reson ance in the transformer. the controller enters burst mode when the output power falls below a given level. the h f c 0 3 0 0 features various protections su ch as thermal shutdown, v cc under-volt age lockout , overload protection, sh ort-circuit pr otection, an d over-voltage protection. the h f c03 0 0 is availa ble in soic- 7 p a ckag e. features ? variable off-time, current mode control ? universal main supply operation (85vac to 265vac) ? frequency foldback a s load lighte ns ? peak-current compression to red u ce transformer noise ? active-burst mode for low standby power consumption ? internal hig h -voltage current source ? internal 200 ns leading edge blanking ? thermal sh utdown (auto restart with hysteresis) ? vcc under-voltage lockout with hysteresis ? over-voltage protection on vcc pin ? timer-based overload protection ? short-circuit protection ? natural spectrum shaping for improved emi performance appli c ations ? battery cha r ger for portable electro n ics ? standby po wer supply ? switched-mode power supplies f o r m p s g r e e n st at us, pl eas e vis it mp s we bs it e un de r q u al it y assu ra nce . ?mp s ? an d ?t he f u ture o f ana l o g ic t e chno lo gy ? ar e re gi ste r ed tr ade ma r ks o f monolithic power systems, inc. http://
HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 2 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. typical applicaion in pu t 8 5 v a c - 2 6 5 v a c * * * t1 output HFC0300 1 2 3 4 5 6 8 fset hv gn d comp cs vcc drv HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 3 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) HFC0300hs soic-7 HFC0300 -40c to +125c for ta pe & reel, add suffix ?z (e.g. hf c03 0 0 h s?z); for rohs co mpliant pa ckaging, ad d su ffix ?lf (e.g. hfc030 0hs ?lf?z ) package reference absolute m a xi mum ratings (1) hv breakdown voltage .............. -0.7v to +700v vcc, drv t o gnd ........................ -0.3v to +30v drv to gnd ................................. -0.3v to +18v fset, comp, cs to gnd .............. -0.3v to +7v continuous power dissipation (t a = +25c) (2) soic-7 ??????????????....1.3w junction te mperature ............................... 150c thermal sh ut down .................................. 150c thermal sh ut down hysteresis .................. 25c lead temperature .................................... 260c storage temperature .............. -60c to +150c esd capabi lity human body model (all pins except drain) ........................................... 2.0kv esd capabi lity machine model ................. 200v recommended operati on conditions (3) maxi mum j unction temp. (t j ) ............... +125c operating vcc range ........................ 8.2v to 20v thermal resistance (4) ja jc soic-7 .................................... 96 ...... 45 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction temperatu r e t j (max), the junction-to- ambient therm a l resistance ja , a nd the a m bient t e mperatu r e t a . the maximu m allow a ble con t inuous po w e r di ssipation at an y ambient te mperatu r e is ca lculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation w ill cause ex cessive die tempe r ature, and t h e regulator w ill g o into thermal shutdo w n . inte rnal thermal shutdo w n circuitr y pr otects the device from permanent damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb. dr v cs gnd copm hv vcc fset 1 2 3 4 8 6 5 t op view soic-7 HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 4 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved electri c al characteristi cs v cc =12v, t a =25c, unless otherw i s e noted. parameter sy mbol conditio n s min t y p max unit start-up current source (pin hv) supply cu rre nt from pin hv i hv v hv =400v, vc c= 6v 2 ma brea k-do wn voltage v br 700 v off-state hv lea kag e cu rrent i leak v hv =400v, vcc=10v 10 17 a supply voltage management (pin vcc) vcc in cre a si ng level whe r e the cu rren t source turns off vcc off 10.7 11.7 12.7 v vcc decre a sing level whe r e the cu rren t source turn s on vcc on 7.6 8.2 8.8 v vcc re-ch a rge level whe r e prote c tion s occu rs v ccr 5.0 5.5 6.0 v vcc decre a sing level whe r e latch-off phase ends vcc latch 3.0 v internal ic consumption , 1nf loa d on drv pin icc fs = 6 5khz , vcc=12v 1.3 ma internal ic consumption, latch off pha s e icc latch vc c= 6v 500 a risi ng voltag e thre sh old o n vcc whe r e controlle r lat che s off (ov p ) v ovp 22.5 24 25.5 v integration ti me con s train t on the ovp comp arator t int 20 s timing capacitor(pin fset) minimum volt age on fset capa citor v fset min 0.82 0.88 0.94 v maximum vol t age on fse t capa cito r v fset ma x 3.2 v source curre n t i fset 23 28 33 a fset capa ci tor disch a rge time (active at drive turn -o n) t disch 0.6 s feedback management (pin comp) over loa d protection set point v olp 0.80 0.85 0.90 v over loa d protection dela y time t olp c fset =330 pf 74 ms comp decre a sin g level where the cont rolle r enters the burs t mode v burh 3.0 3.2 3.4 v comp incre a s ing l e vel wh ere the controller leave s the burst mo de v burl 2.9 3.1 3.3 v current sampling management (pin cs) short-circuit comp arator l eadin g -edg e blankin g t leb1 150 ns curre n t-sen s e comp arator leadin g -ed g e blankin g t leb2 200 ns maximum cu rre nt-sen se comp arator l i mit v limit v co m p =1v 0.45 0.5 -0.55 v short-circuit protectio n point v scp v scp 1.0 v HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 5 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved electri c al characteristi cs (continued) v cc =12v, t a =25c, unless otherw i s e noted. parameter symbol conditions min typ max unit driving signal (pin drv) sourcing re sistor r h 10 ? sinking re sistor r l 3 ? v drive clamp v drive vcc=18v 13.7 v pin functio n s soic-7 pin # nam e des c ription 1 drv drive. output of the drive signal. 2 cs current sense input. 3 gnd ground. 4 comp switchin g freque ncy set. a feedback volt age of 0.85v will trigge r overl o a d protection, and a feedback voltage of 3. 1v will trigger a burst mode operation. 5 fset frequency set. maximum switching frequency set by a capacitor. 6 vcc ic supply. conne cted to an extern al b u lk cap a cito r. if an auxiliary windin g bri n g s this pin above 24v, the controller latches off. 8 hv high-voltage source. input for t he start-up high voltage current source. HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 6 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved typical performanc e characteristics 1.5 1.7 1.9 2.1 2.3 2.5 2.7 -40 -20 0 20 40 60 80 100 120 11 11.25 11.5 11.75 12 -40 -20 0 2 0 40 60 80 100 120 v cch (v) v ccl (v) 7.5 7.75 8 8.25 8.5 -40 -20 0 2 0 4 0 6 0 8 0 1 00 120 0.78 0.8 0.82 0.84 0.86 0.88 -40 -20 0 2 0 4 0 6 0 80 100 120 v olp (v) 68 70 72 74 76 78 -40 -20 0 2 0 4 0 6 0 80 100 120 t ocp (ms) 23.5 23.7 23.9 24.1 24.3 24.5 -40 -20 0 2 0 4 0 6 0 8 0 100 120 v ovp (v) 0.86 0.865 0.87 0.875 0.88 -40 -20 0 20 4 0 6 0 8 0 100 120 fset min (v) 26 27 28 29 30 -40 -20 0 20 4 0 6 0 8 0 100 120 0.48 0.485 0.49 0.495 0.5 0.505 0.51 -40 -20 0 2 0 4 0 6 0 8 0 100 120 i peak (v) HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 7 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved typical performanc e characteristics (continued) comp increasing level at which the controller enters the burst mode vs. t emperature comp decreasing level at which the controller leaves the burst mode vs. temperature scp point vs. temperature 0.85 0.87 0.89 0.91 0.93 0.95 -40 -20 0 20 40 60 80 100 120 i peak (v) 3.17 3.19 3.21 3.23 3.25 -40 -20 0 2 0 40 60 80 100 120 v burh (v) 3.08 3.1 3.12 3.14 3.16 -40 -20 0 2 0 4 0 60 80 100 120 v burl (v) HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 8 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved block diagram c s ( 2 ) c o m p ( 4 ) v c c ( 6 ) d r v ( 1 ) h v ( 8 ) f s e t ( 5 ) pow e r management start up unit internal power supply driving signal management fault management ovp peak current compression burst mode control frequency control olp current comparator g n d ( 3 ) otp figure 1: functional block diagram HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 9 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. operation the HFC0300 incorp orates all t he necessa ry features to build a relia ble switched-mode po wer supply (smps). its high level of integration requires fe w external components. based on a fixed peak current technique, t he controlle r decreases it s frequency with the decreasing load to minimize switching loss. whe n the output power falls below a g i ven level, the controller enters burst mode. it also has better e m i performance because the swit ch ing frequen cy varies with the natural b u lk ripple voltage. frequenc y foldback a capacitor connected to the fset pin sets the frequency at the end of charging. this capacitor charges from a constant current source and its voltage is compared with an internal threshold fixed by comp voltage (see figure 2). when this capacitor voltage reaches threshold, the capacitor discharges rapidly down to 0v, and a new period starts after a 0.6 s delay (see figure 3). s r _ q q 28a 3.3v v offset 0.88v 0.6s pulse drive fset comp vc c figure 2: v o lt age-controlled oscillation maximum frequency m i nim um fr e quency i f set =2 8 a vf s e t controlled by the comp voltage pout dec r eas e pout increase figure 3: comp-v olt a g e?adjusted sw itching frequenc y start-up an d under vo ltage lock-out initially, the internal h i g h voltage current source drawn from the high-voltage (hv) pi n powers the ic. the ic starts switch ing and the internal high - voltage current source turns off as soon as the voltage on vcc reaches 11.7 v . then th e auxiliary winding of the transformer supplies t h e ic before the vcc volta ge falls back below 8.2v. otherwise, the switching pulse st ops and th e high-voltage current sou r ce turns on again. figure 4 sh ows the typical waveform with vcc under-voltage lockout (u vlo). v cc h =11 . 7v v ccl =8.2v v cc in tern a l c u rre nt so ur ce dr iv i ng signa l on off th e au xi l i a r y w i n d in g t a k e s ov er figure 4: vcc under-v olt age lockout the lower th resho l d of v c c uvlo g oes f r om 8 . 2 v to 5. 5v w h en fa ult co ndition s ha p pen , su ch as over- l oa d pr ote c t i o n (ol p ), over -volt age pro t e c t i on (ovp), and over-t emper atur e pro t e c t i on (o tp). over-volta ge protection by monitori ng the vcc pin with a 20s time- constant filt er, the hf c0300 goes into latch ed fault cond ition when ever an over-volt age condition o ccurs?if vcc goes above 24v, typically. the controller stays fully latched in this position unt il the vcc is cycled down to 3.0v, e.g. when the user unplugs t he power supply from th e main input and re-plugs it. over-load protection in a flyback converter, the maxi mum output power is limited by t he maxi mu m switching frequency and primary peak current. as the primary pea k current is constant, t he maxi mu m power is limited by maximu m frequency. when the switchin g frequency reaches th e maxi mu m, HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 10 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. the output voltage decreases if t he load continues to increase. comp then drops belo w the over-load protection (olp) point becau se feedback is equivalent to an open circuit. by continuously monitoring the comp, when t h e comp voltage drops below 0.85v?which is considered an error?the timer start s counting. i f the error fla g is removed, the timer resets. if th e timer reaches completion at the delay time determined by the fset capacitor (for exampl e, 74ms at c fset =3 30pf ) , olp takes place. this timer avoid s triggering olp whe n the power supply is a t start-up o r load tran sition pha se. therefore t he power supply should start-up in less t han o v er load pr otection de lay time, as determined by the following equation : fset de la y c t7 4 m s 33 0 p f ?? short circu i t protection the hfc03 00 shuts down when th e cs voltag e rises higher than 1v using short-circuit protectio n (scp). as soon as the fault disappears, the power supply resumes operation. during scp, the vcc uvlo lower t h reshold go es from 8.2 v to 5.5v. thermal shutdow n the HFC0300 shuts d o wn switching when the inner temperature exceeds 150 c to prevent damagi ng hig h temperatu r es . as soon as the inne r temperature drops below 125 c , the powe r supply resu mes operation. during the thermal shutdown (tsd), the vcc uvlo lo wer threshold goes from 8.2v to 5.5v. peak curre nt compression as the load becomes lighter, th e frequency decreases a nd may ent er the audible range. to avoid exciting mechanical resona nces in th e transformer and generating acoustic noise, t h e HFC0300 reduces the peak curr ent as pow er goes down and thus red u ces noise issues. figure 5 sh ows the cur v e of peak current versus comp. comp(v) pea k curr ent(v) 0. 5 0. 1 6 7 2. 1 3. 1 0.9 3.2 c ons t ant p eak cur r ent pe ak cu r r en t compr e ss i o n bu rs t mod e figure 5: peak current vs. comp burst ope r ation the HFC0300 enters burst-mode operation to minimize power dissip ation in no load or lig ht load condit i ons. as th e load decreases, the comp voltage increase s ; the ic stops switchin g when the comp voltage increa ses over the threshold, v bruh = 3.2v. the output voltage then drops, which causes the comp voltage to decrease fu rther. once the comp voltage falls below the threshold v brul = 3.1 v , switching resumes and the comp voltage then oscilate s. the burst mode operation altern ately enables and disable s switching cycle of the mosfet. leading-edge blanking in order to a v oid the pre m ature termination of th e switching p ulse due to the parasitic capacitance, an internal leading-edg e blanking (leb) unit is employed b e tween the cs pin an d the curre nt comparator input. during the blanking time, the current comparator is d i sabled and can not turn off the external mosf et. figure 6 shows the leading-edg e blanking. t leb =200ns v lim i t t figure 6: leading-edge blanking HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 11 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. start vcc>11.7v t>t olp and olp=logic high internal high voltage current source on y n soft start monitor v comp monitor vcc v comp <0.85v 0.85v HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 12 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. 11 . 7 v 8. 2 v 5.5v vcc dr iv er fa ult fla g o v p fa ul t o c c u rs h e re d r i ver pluses re gu l a t i on oc c u rs he re high voltage current source start up n o rm al ope ra ti on normal o p er ati o n nor m al ope rat i on olp fa ult oc c u rs he re on off over voltage occurs here no rm a l operation o t p fa ul t o c c urs here n o r m al o p e r at i o n un pl u g f r om main in put norm al op erati o n norm al op erati o n ol p delay figure 8: signal changes in the presence of different fa ult s HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 13 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. appli c ation information design keys of HFC0300 current se nse resistor section the peak cu rrent level is internally set to 0.5v, so the current-sense resist or sets the primary-side peak curre nt, which d e termines the operatio n mode of th e converter?such as ccm, bcm or dcm. if po wer supply i s designed to operate at bcm at low-line input, i t will operat e at dcm a t the high lin e and the same load condition. th e magnetizing inductor current (refle c ted on th e primary side) and the dr ain-source v o ltage (v ds ) of the primary mosfet is shown in figure 9. in d u ct o r current (a) v ds high line low lin e inductor current (a) tsecond t tsecond i pr i m a r y i s e co nd ar y / n 0. 5v /r sens e v ds i pr i m a r y i secondary / n 0. 5v /r sens e figure 9: inductor current and v o lt age of primary mosfet the time d u ration of t he seconda ry current can be determined by equation (1): m peak se c o li t nv ? ? ? (1) where l m is the primary magnetizin g inductance, i peak is the pr imary peak current, and n is the tur n ratio of the transformer. i peak remains the s a me a t under different inputs and with the same output, so the time duration of secondary current is the sam e . the switchin g period can be calcu l at ed by: peak sec o ni t t 2i ? ? ? ? (2) from equation (2), the switching p e riod remains the same at different in puts with th e same out put condition. since the primary-side s w itch on ti me decreases with the in cr easing in put voltage, then the higher the input line voltage, the deepe r discontinu o u s current mode (dcm) it will enter. usually, the paramete r s are designed for the minimu m in put conditio n to guarantee that the converter can deliver the required maxi mu m output power. since n is pre-determined, if the power supply is designed to operate at boundary current mode (bcm) at the low line, t he peak cur r ent can be calculated a s : o pe ak _ b c m 2i i n( 1 d ) ? ? ?? (3) where d is t he duty ratio of the switching. then: of in o f (v v ) n d v( v v ) n ?? ? ? ?? (4) if the peak current set by the c u rrent-sense resistor is la rger than i pea k _ b c m , the p ower supply will enter d c m. on the other hand , if the pea k current set by current sense resisto r is less tha n i peak_bcm , th e power su pply will en ter ccm, as shown as figure 10. he re, we define k depth as the depth of ccm. v a lle y d epth p eak i k i ? (5) HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 14 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. i m o sfet i peak i valley figure 10: primary cu rrent at ccm so the peak current can be determined as: o p eak _ c c m depth 2i i (1 d ) (1 k ) n ? ? ?? ? ? (6) usually, bcm is preferable at power levels belo w 40w, and ccm is preferable at power levels higher than 40w: the higher the power delivered, the deeper the ccm adopted for higher efficiency and b e tter thermal performance at full load . for exa m ple, for a 90w power supply, k depth should be around 0.5. the converter oper ation mode must be determined with each p o wer supply specif icatio n given; i.e. determine the k depth . i pea k and i v a lle y as calculated by equations (3) through (6). select the current sense resisto r using equa tion (7). peak se nse pe ak v r i ? (7) where v peak is th e peak voltage threshold of th e current resistor; a consta nt 0.5v for HFC0300. chose the current resist or with the proper power rating based on the power loss give n in equatio n (8) peak val l e y 22 s ens e peak val l ey sense ii 1 p[ ( ) ( i i ) ] d r 21 2 ? ?? ? ? ? ? (8) design of c fset and ol p function the capacit or c fset sets the maximum frequency as shown in equation (9). this capacitor is charged by a constan t -current so urce shortly after the primary side switch turn s on (about 0.6s delay), and its volt age is compared with th e comp volt age from fe edback loo p (see figure 11). when the capacitor voltage reaches thresho l d, the capacito r rapidly discharges do wn to 0v, a n d a new perio d starts. an internal delay of about 0.6s delay before c fset charges again fully discharges the voltage at the fs et pin, (se e figure 12). thus the switching frequency is regulated b y the feedb ack loop like a voltage - controlled o scillation (v co). max fs e t 1 28 u a ( 0 .6 us ) f c 0. 88 v ?? ? (9) where f ma x is the ma ximum freque ncy set by the capacito r connected to fset pin. s r _ q q 28a 3.3v v offset 0.88v 0.6s pulse drive fset comp vcc figure 1 1 : schematic for v o lt age-controlled oscillation maximum frequency m i nim u m fr equ ency i f set = 28 a vf set controlled by the comp voltage po ut d e cr ease pout i n cr ease figure 12: sw itching frequenc y as adjusted b y comp v o lt age as describe d in the section above, the switchin g frequency reaches its maxi mum a t low line and full load. th is frequency, defined as f s (65khz in this case). set the ma ximu m freq uency (f ma x ) at 110% f s . the frequency increases with t h e increasing output power. when t he frequen cy reaches it s maxi mum?set by c fset ?the over- power limit drops the o u tput voltage, saturatin g comp, and drops the olp threshold (0.85v). the olp u s es a uniq ue digital timer metho d : when comp is less th an 0.85v a nd raise s a n error flag, the timer st arts countin g. if the error flag is removed, the timer resets. if the time r overflows after reaching 6000, olp triggers. this timer duration avoids t r iggering th e olp whe n HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 15 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. the power supply is at start-up or load transitio n phase. ther efore, set t he output v o ltage in le ss than 6000 switching cycles during st art-up. ramp com pensation circuit if the power supply operates in ccm and th e duty cycle is larger than 0.5, add a ramp compensation circuit to avoid harmonics in pea k current mode contr o l. usually , the ra mp compensation rate is selected a s per equatio n (10) o sense m vn r k l ?? ?? ? (10) where: ? ? is the coefficient which is usually 0.5 to 1.0 ? r sense is t he value of primary sense resistor for applica t ions using the HFC0300, use t he ramp compe n sation circuit shown in figure 13 . gnd cs drv HFC0300 1 2 3 4 5 6 8 fset hv vc c comp vc c cs 510 k 33pf 1k 30 k r1 r2 r3 c1 figure 13: ramp com pensation circuit equation (11) estimates the compensation rate o f the above circuit : dr v 1 2 vr k* r ? ? (11) where v drv is the drive voltage 31 r* c ? ? select ? to be larger than the switchin g period so that the ramp is approximately linear. design summary figure 14 shows a detailed refere nce design of the off-time controlled flyback converter using t h e HFC0300. the input voltage i s 90vac to 265vac an d the output is 24v/1.5a. the transformer used in this design has a turn ratio of 84:14:8 (n p : n s : n aux ) with a primary inductance of 818 h. the core is ee25. figure 15, figure 16, and table 1 winding ordershow wiring schematics. HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 16 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. pgnd 4 5 3 1 pgnd pgnd agnd pgnd 6/7 9/10 agnd cn2 HFC0300 cn1 1a f1 lx1 ns np np - a u x ee25 t1 co m p 4 fset 5 gn d 3 vcc 6 cs 2 nc 7 dr v 1 hv 8 u1 gbu406 bd1 5 rt1 2.2m r3 2.2m r5 150k r2 a 150k r2 b 51k r2 nc rf 10 r6 20k r7 1k r8 10k r1 1 r3c 1 r3b 1 r3a 1k r13 1 r14 11.3k r1 6 nc r1 7 20 r1 1 a 20 r1 1 b c1 4.7nf c2 c5 1nf c7 c8 3.3nf c9 c11 c12 c13 fr 1 0 7 d2 tl431k u3 u2 pc8 17 a ap2761i-a q1 97 .6 k r15 4.02k r1 2 2. 2n f cy3 cx 1 b1 1 0 0 1 2 d3 3.3 r4 1 2 c3 c6 c10 l1 1 3 2 v 40120c d1 figure 14: schematic of off-t ime fl y back converter w i th HFC0300 sec. n 1 n 2 n 4 3 4 5 2 1 n 3 9 7 pri. 6 10 teflo n tube figure 15: connection diagram HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 17 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. t able 1 w i nding order tape (t) winding edge tape (pri.) terminal (st a rt -end ) edge tape (sec.) wire size ( ) turns ( t ) 1 n1 2mm 3->2 2mm 0.3mm*1 42 1 n2 2mm 5->4 2mm 0.2mm*1 8 3 n3 2mm 9,10->6,7 2mm 0.3mm*5 14 3 n4 2mm 2->1 2mm 0.3mm*1 42 3 experimental verification a physical prototype based on figure 13 was used to verify both the design procedure presented in this a pp lication not e, and th e performance. the input ranged bet ween 90vac and 265vac, and the output was at 24v/1.5a. the converter operates in bcm at 90vac inpu t and full load . figure 17 and figure 18 the current and drain voltage wa veforms of the prima r y mosfet. figure 19 shows the burst mo de function of t he controller at light load . to minimize power dissipation at no load or ligh t load, the h f c0300 enters burst-mode operation. as the load decrease s , the comp voltage increases. the hf0300 skip s switching cycle s when the comp voltage increa ses over the threshold v burh = 3.2v. the output voltage drops, causing the comp voltage to decrease again. once the c o mp voltage falls below the thre shold v burl = 3.1 v , switching resumes. the comp voltage then rings. the burst mo de operation alternately e nables and disables switching cycle s of the mosfet thereby reducing switching lo ss in the no loa d or light loa d condition s. figure 20 shows over-load prote c tion. whe n comp is low, the contr o ller stop s switching aft e r 6000 switching cycles (about 100ms for thi s application) figure 21 shows the measured efficiency. fro m the efficiency curve, the efficiency is still h i gh at light load condition du e to de crea sed swit ching frequency. also the p o wer consu m ption at no load is given in table 2. i n burst mode, the power loss with n o load is very small, even with high line input. n1 n2 n3 n4 1t 3t 3t 2mm pri. side 2mm sec. side 1t tape: 3 t figure 16: winding diagram HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 18 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. figure 17: drain curre n t and v o lt age of mosfet at low-line input (90v ac); ch2 - cs, ch3, v ds cs v ds v ds cs figure 18: drain current and voltage of mosfet at high-line input (230vac); cs2 - cs, ch3 - v ds HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 19 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved comp drv vout iout figure 19: burst mode; ch2 - comp, ch3 - drv figure 20: overload protection; ch1 - v out , ch2 - drv, ch4 - i out HFC0300? variable off time cont roll er hfc030 0 rev. 1 . 0 www.monolithicpower.com 20 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. t able 2: no-load loss at different line v o lt ages input v oltage (v ac , rms ) 90 115 230 265 po w e r loss (mw) 74.4 77.2 110.1 121.9 72.00% 74.00% 76.00% 78.00% 80.00% 82.00% 84.00% 86.00% 88.00% 90.00% 0 .1 0.2 0.3 0.4 0.5 0. 6 0.7 0.8 0.9 1 1 .1 1. 2 1.3 1.4 1.5 outp ut curre nt io(a) effici ency(%) vin=11 5vac vin=230vac figure 21: measured efficiency HFC0300? variable off time cont roll er notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. hfc030 0 rev. 1 . 0 www.monolithicpower.com 21 9/23/2011 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. package informati o n soic-7 0. 01 6( 0. 4 1 ) 0.050(1.27) 0 o -8 o detail "a" 0. 0 10( 0. 25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pi n 1 i d 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) se a t i n g pl a n e 0.004(0.10) 0.010(0.25) 0. 1 89 ( 4 . 80) 0. 1 97 ( 5 . 00) 0. 0 53( 1 . 35 ) 0. 0 69( 1 . 75 ) to p vi ew fr ont view 0. 228(5.80) 0.244(6.20) si de view 14 85 re co m m e nd e d l a nd p a t t e r n 0.21 3 ( 5 . 4 0) 0.063( 1 . 60) 0.0 5 0(1.27) 0.024( 0 . 61) no t e : 1 ) co nt r o l d i m e ns i o n i s i n i nch e s . d i m e n s io n in b r a c k e t i s i n m il l i m e t e r s . 2 ) p a ck a g e l e ng t h d o e s no t i n cl u de m o l d f l a s h , p r o t ru s i o n s o r g a t e b u r r s . 3 ) pa c k a g e w i d t h d o es n o t i n c l u d e i n t e r l ea d f l a sh o r p r o t r u s io n s . 4 ) l e a d co p l a n ar it y ( b o tto m o f l e a d s a f te r f o r m i n g ) s h a l l b e 0 . 0 0 4 " in ch e s m a x . 5 ) j e d e c re f e r e nce is m s - 0 1 2 . 6 ) dr aw i ng i s n o t t o s c al e . 0.010(0 . 25) b s c gaug e p l ane |
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